Referring to FIG. 1, a conventional, six transistor static RAM cell 10 is shown constructed from Gallium Arsenide (GaAs), MESFETS. Cell 10 comprises two identical, generally parallel, cross-coupled branches indicated at 12, 12'. For purposes of explanation, identical elements in each branch will be indicated with identical reference numerals, the numerals of the elements in the right branch being primed.
Describing now the structure of branch 12, a depletion mode load transistor, indicated at 14, is connected with its drain-source path in series between a pair of nodes A, B, and with its gate connected to circuit node B. Node A is adapted, for example through the use of appropriate metallization, for connection to a source of drain bias potential indicated as VDD An enhancement mode active transistor 18 is connected with its drain-source path in series between circuit node B and a circuit node C, the latter circuit node being adapted for connection to a circuit ground. An access transistor 20 is connected at its source to circuit node B, its drain functioning to receive the bit-line signal (BL), and its gate functioning to receive the word-line signal (WL).
Branches 12, 12' are connected at the drains of load transistors 14, 14' to circuit node A and at the sources of active transistors 18, 18' to circuit node B. Branches 12, 12' are further cross-connected between nodes B, B' and the gates of transistors 18', 8, respectively.
In operation, transistors 14, 14', 18, 18' function in a well known manner as a bistable flip-flop, controlled by word line signal WL, to read or write complementary voltage levels utilizing bit-line signals BL, BL-bar.
A disadvantage of above described cell 10 is that of high current consumption when word-line signal WL is not enabled (i.e. when word-line signal WL is logically low and cell 10 is in the standby mode of operation). For purposes of explaining this undesirable current consumption, it is necessary for the reader to understand that the gate-source junction of a MESFET device functions as a Schottky diode. Of particular interest with respect to the operation of cell 10 is the Schottky diode formed between the gate of active transistor 18 and circuit node C, the diode being indicated in phantom at SD1.
Continuing to explain the undesirable current consumption of cell 10 in the standby mode of operation, it will be assumed for purposes of explanation that word-line signal WL nd bit-line signals BL, BL-bar have been activated, in a conventional manner, to turn active transistor 18 on, and active transistor 18' off. This status causes a low side load current I1 to flow through branch 12. The gate of active transistor 18 is biased at a voltage level determined by the clamping action of Schottky diode SD1, and a second, high side load current I2 flows along the indicated path through branch 12' and Schottky diode SD1. This load current I2 constitutes the undesirable current component present in the standby mode of operation.